december 2009 ? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsusb45 ? rev. 1.0.6 fsusb45 ? hi-speed usb2.0 (480mbps) switch with dedicated charger port detect fsusb45 ? hi-speed usb2.0 (480mbps) switch with dedicated charger port detect features ? low on capacitance: 7.0pf typical ? low on resistance: 3.9 ? typical ? low power consumption: 1 a maximum - 15 a maximum i cct over an expanded voltage range (v in =1.8v, v cc =4.3v) ? wide -3db bandwidth: > 720mhz ? packaged in: - 10-lead micropak? (1.6 x 2.1mm) - 10-lead umlp (1.4 x 1.8mm) ? 8kv esd rating, >16kv power/gnd esd rating ? power-off protection on all ports when v cc= 0v - d+/d- pins tolerate up to 5.25v applications ? cell phone, pda, digital camera, and notebook ? lcd monitor, tv, and set-top box important note: for additional performance info rmation, please contact analogswitch@fairchildsemi.com . description the fsusb45 is a bi-directional, low-power, two-port, hi-speed, usb2.0 switch. configured as a double-pole, double-throw (dpdt) switch, it is optimized for switching between two hi-speed (480mbps) sources or a hi-speed source and a full-speed (12mbps) source. the fsusb45 is compatible with the requirements of usb2.0 and features an extremely low on capacitance (c on ) of 7.0pf. the wide bandwidth of this device (720mhz) exceeds the bandwidth needed to pass the third harmonic, resulting in signals with minimum edge and phase distortion. superior channel-to-channel crosstalk also minimizes interference. the fsusb45 contains special circuitry on the switch i/o pins for applications where the v cc supply is powered-off (v cc =0), which allows the device to withstand an over-voltage condition. this device is designed to minimize current consumption even when the control voltage applied to the sel pin is lower than the supply voltage (v cc ). this feature is especially valuable to mobile applications, such as cell phones, allowing for direct interface with the general-purpose i/os of the baseband processor. an additional feature is the detection of the 1,1 state on d+/d- to signal an interrupt (int) to the processor when entering a dedicated charging port mode of operation. figure 1. analog symbol ordering information part number top mark operating temperature range eco status package fsusb45l10x ja -40 to +85c rohs 10-lead micropak? 1.6 x 2.1mm, jedec mo-255b FSUSB45UMX jb -40 to +85c green 10-lead, quad, ultrathin molded leadless package (umlp), 1.4 x 1.8mm micropak? is a trademark of fairchild semiconductor corporation. for fairchild?s definition of eco status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html .
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsusb45 ? rev. 1.0.6 2 fsusb45 ? hi-speed usb2.0 (480mbps) switch with dedicated charger port detect pin assignments 5 4 3 21 67 8 9 10 int vcc sel hsd1+ hsd2+ d+ hsd1- hsd2- d- gnd figure 2. pad assignment for micropak (top through view) figure 3. pin assignments for umlp (top through view) pin definitions micropak? pin # umlp pin # name description 9 8 int interrupt signaling output pin 1 10 sel switch select 4, 6 3, 5 d+, d- usb data bus 2, 3, 7, 8 1, 2, 6, 7 hsdn+, hsdn- multiplexed source inputs 5 4 gnd ground truth table sel switch connection d+ d- int output l d+, d-=hsd1+, hsd1- 1,1 low h d+, d-=hsd2+, hsd2- 0x, x0 high
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsusb45 ? rev. 1.0.6 3 fsusb45 ? hi-speed usb2.0 (480mbps) switch with dedicated charger port detect absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v cc supply voltage -0.5 +5.5 v v cntrl dc input voltage (s) (1) -0.5 v cc v v sw dc switch i/o voltage (1) -0.50 5.25 v i ik dc input diode current -50 ma i out dc output current 50 ma t stg storage temperature -65 +150 c esd human body model, jedec: jesd22-a114 all pins 7 kv i/o to gnd 8 power to gnd 16 charged device model, jedec: jesd22-c101 2 note: 1. the input and output negative ratings may be exceeded if the input and output diode current ratings are observed. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. unit v cc supply voltage 3.0 4.3 v v cntrl (2) control input voltage (sel) 0 v cc v v sw switch i/o voltage -0.5 v cc v t a operating temperature -40 85 c note : 2. the control input must be held high or low and it must not float.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsusb45 ? rev. 1.0.6 4 fsusb45 ? hi-speed usb2.0 (480mbps) switch with dedicated charger port detect dc electrical characteristics all typical value are at 25c, v cc =3.3v unless otherwise specified. symbol parameter conditions v cc (v) t a =- 40oc to +85oc units min. typ. max. v ik clamp diode voltage i in =-18ma 3.0 -1.2 v v ih input voltage high 3.0 to 3.6 1.3 v 4.3 1.7 v v il input voltage low 3.0 to 3.6 0.5 v 4.3 0.7 v v oh output voltage high i oh =-2ma 3.0 to 3.6 2.4 v 4.3 2.4 v ol output voltage low i ol =2ma 3.0 to 3.6 0.25 v 4.3 0.25 i in control input leakage v sw =0 to v cc 4.3 -1 1 a i nc(off), i no(off) off state leakage hsd1n or hsd2n=0v, 3.6v or floating, d+/-=0 or 3.6v 4.3 -2 2 a i dn(on) on state leakage hsd1n or hsd2n=0v, 3.6v or floating, d+/-=0 or 3.6v 4.3 -2 2 a i off power-off leakage current (all i/o ports) v sw =0v to 4.3v, v cc =0v figure 5 0 -2 2 a r on hs switch on resistance (3) v sw =0.4v, i on =-8ma figure 4 3.0 3.9 6.5 ? r on hs delta ron (4) v sw =0.4v, i on =-8ma 3.0 0.65 i cc quiescent supply current v cntrl =0 or v cc , i out =0 4.3 1.0 a i cct increase in i cc current per control voltage and v cc v cntrl =2.6v v cc =4.3v 4.3 10.0 a v cntrl =1.8v v cc =4.3v 4.3 20.0 a notes : 3. measured by the voltage drop between hsdn and dn pi ns at the indicated current through the switch. on resistance is determined by the lower of the voltage on the two (hsdn or dn ports). 4. guaranteed by characterization.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsusb45 ? rev. 1.0.6 5 fsusb45 ? hi-speed usb2.0 (480mbps) switch with dedicated charger port detect ac electrical characteristics all typical value are for v cc =3.3v at 25c unless otherwise specified. symbol parameter conditions v cc (v) t a =- 40 to +85c units min. typ. max. t on turn-on time s to output r l =50 ? , c l =5pf v sw =0.8v figure 6, figure 7 3.0 to 3.6 13 30 ns t off turn-off time s to output r l =50 ? , c l =5pf v sw =0.8v figure 6, figure 7 3.0 to 3.6 12 25 ns t pd propagation delay (5) c l =5 pf, r l =50 ? figure 6, figure 8 3.3 0.25 ns t bbm break-before-make r l =50 ? , c l =5pf v sw1 =v sw2 =0.8v figure 12 3.0 to 3.6 2.0 6.5 ns t plh/hl int propagation delay (5) r l =50 ? , c l =5pf 3.0 to 3.6 10 ns o irr off isolation r l =50 ? , f=240mhz figure 14 3.0 to 3.6 -30 db xtalk non-adjacent channel crosstalk r l =50 ? , f=240mhz figure 15 3.0 to 3.6 -45 db bw -3db bandwidth r l =50 ? , c l =0pf figure 13 3.0 to 3.6 720 mhz r l =50 ? , c l =5pf figure 13 550 mhz note : 5. guaranteed by characterization. usb hi-speed-related ac electrical characteristics symbol parameter conditions vcc (v) t a =- 40 to +85c units min. typ. max. t sk(p) skew of opposite transitions of the same output (6) c l =5pf, r l =50 ? figure 9 3.0 to 3.6 20 ps t j total jitter (6) r l =50 ? , c l =5pf, t r =t f =500ps (10-90%) at 480mbps (prbs=2 15 ? 1) 3.0 to 3.6 200 ps note : 6. guaranteed by characterization. capacitance symbol parameter conditions t a =- 40 to +85c units min. typ. max. c in control pin input capacitance v cc =0v 1.5 pf c out int pin output capacitance v cc =0v 2.5 pf c on d+/d- on capacitance v cc =3.3v, f=1mhz figure 11 7.0 7.9 pf c off d1n, d2n off capacitance v cc =3.3v figure 10 2.0 pf
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsusb45 ? rev. 1.0.6 6 fsusb45 ? hi-speed usb2.0 (480mbps) switch with dedicated charger port detect test diagrams select hsd n dn v sel = 0 orv cc i on v on r on = v on /i on gnd v sw gnd sw figure 4. on resistance figure 5. off/on leakage r l ,r s ,andc l are functions of the application environment (see ac tables for specific values) c l includes test fixture and stray capacitance. r l c l hsd n dn gnd gnd r s v sel v sw gnd v out v out t rise =2.5ns gnd v cc 90% 90% 10% 10% t fall = 2.5ns v cc /2 v cc /2 input ? v /oe ,v sel output- v out 90% v oh v ol t on t off 90% v ?v v ? figure 6. ac test circuit load figur e 7. turn-on / turn-off waveforms input output v oh v ol 50% 50% 50% 50% 400mv t phl t plh 0v t rise = 500ps -400mv 90% 90% 10% 10% t fall =500ps 0v output t phl +400mv t plh figure 8. propagation delay (t r t f ? 500ps) figure 9. intra-pair skew test t sk(p) v sel = 0 or v cc hsd n capacitance meter s hsd n v sel = 0 or v cc hsd n capacitance meter s hsd n figure 10. channel off capacitance figure 11. channel on capacitance
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsusb45 ? rev. 1.0.6 7 fsusb45 ? hi-speed usb2.0 (480mbps) switch with dedicated charger port detect test diagrams (continued) v cc 0.9*v out v cc /2 t bbm 0v v out input - v sel 0.9*v out t rise = 2.5ns 90% 10% c l hsd n r l dn gnd gnd r s v sel v sw1 gnd v out v sw2 gnd - - r l ,r s ,andc l are functions of the application environment (see ac tables for specific values) c l includes test fixture and stray capacitance. figure 12. break-before-make interval timing v out gnd gnd r t gnd gnd v s r s network analyzer v sel gnd r s and r t are functions of the application environment (see ac tables for specific values). v in figure 13. bandwidth r s and r t are functions of the application environment (see ac tables for specific values). v out gnd gnd r t gnd gnd v s r s network analyzer r t gnd v sel gnd v in r t off isolation = 20 log (v out / v in ) figure 14. channel off isolation v out gnd gnd r t gnd gnd v s r s network analyzer r t gnd r s and r t are functions of the application environment (see ac tables for specific values). v sel gnd nc v in crosstalk = 20 log (v out / v in ) figure 15. non-adjacent channel-to-channel crosstalk
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsusb45 ? rev. 1.0.6 8 fsusb45 ? hi-speed usb2.0 (480mbps) switch with dedicated charger port detect physical dimensions bottom view top view recommended land pattern side view 2x 2x notes: a. package conforms to jedec registration mo-255, variation uabd . b. dimensions are in millimeters. c. dimensions and tolerances per asme y14.5m, 1994. d. presence of center pad is package supplier dependent. if present it is not intended to be soldered and has a black oxide finish. e. drawing filename: mkt-mac10arev5. 0.10 c 0.10 c 0.10 cab 0.05 c pin1 ident is 2x longer than other lines a b c 0.35 0.25 9x 9x 14 9 6 0.25 0.15 10 5 0.50 0.56 1.62 0.05 0.00 0.05 c 0.55 max 0.05 c 1.60 2.10 (0.35) (0.25) 0.50 10x 10x (0.11) 1.12 1.62 keepout zone, no traces or vias allowed (0.20) (0.15) 0.35 0.25 0.35 0.25 detail a detail a 2x scale 0.35 0.25 0.65 0.55 d all features (0.36) (0.29) 0.56 figure 16. 10-lead micropak? package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsusb45 ? rev. 1.0.6 9 fsusb45 ? hi-speed usb2.0 (480mbps) switch with dedicated charger port detect physical dimensions a. dimensions are in millimeters. b. dimensions and tolerances per asme y14.5m, 1994 top view bottom view recommended land pattern 0.15 c 0.08 c b a c 0.15 c 2x 2x side view seating plane 0.10 c 0.050 3 6 1 0.10 c a b 0.05 c 0.55 max. pin #1 quadrant 10 1.40 1.80 0.40 0.15 0.25 10x 0.45 0.55 0.35 0.45 9x 1.700 2.100 0.400 0.663 0.563 9x 0.225 10x 1 0.152 0.100 0.100 0.500 0.100 detail a pin #1 terminal scale: 2x 1.850 1.450 0.550 0.400 0.225 10x 9x 0.450 optional minimial toe land pattern c. drawing filename: umlp10arev2 figure 17. 10-lead ultrathin molded leadless package (umlp) package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsusb45 ? rev. 1.0.6 10 fsusb45 ? hi-speed usb2.0 (480mbps) switch with dedicated charger port detect
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